Intel QuickPath Interconnect

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The Intel QuickPath Interconnect (QuickPath, QPI)^[1][2][3] is a point-to-point processor interconnect developed by Intel to compete with HyperTransport. Prior to the announcement of the name, Intel referred to it as Common System Interface (CSI). Earlier incarnations were known as YAP (Yet Another Protocol) and YAP+. The development was conducted at Intel's MMDC (Massachusetts Microprocessor Design Center) by members of DEC's Alpha Development Group (acquired by Intel). It replaces the Front Side Bus (FSB) for Desktop, Xeon, and Itanium platforms. Intel first delivered it in November 2008 on the Intel Core i7 desktop processor and the X58 chipset. It is used in the Nehalem-based Xeon 5500, first delivered in March 2009, and it will be used on new Nehalem-based Xeon processors^[4] and Tukwila-based Itanium processors.^[5]

The QPI is an element of a system architecture that Intel calls the QuickPath architecture that implements what Intel calls QuickPath technology.^[6] In its simplest form on a single-processor motherboard, a single QPI is used to connect the processor to the IO Hub (e.g., to connect an Intel Core i7 to an X58.) In more complex instances of the architecture, separate QPI links connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard, allowing all of the components to access other components via the network. As with AMD's Hypertransport, the QuickPath Architecture assumes that the processors will have integrated memory controllers, and enables a non-uniform memory architecture (NUMA).

Each QPI comprises two 20-pair point-to-point data links, one in each direction (full duplex), with a separate clock pair in each direction, for a total of 42 signals. Each signal is a differential pair, so the total number of pins is 84. The 20 data links are divided onto four "quadrants" of 5 links each. The basic unit of transfer is the 80-bit "flit," which is transferred in two clock cycles (four transfers, two per clock.) The 80-bit "flit" has 8 bits for error detection, 8 bits for "link-layer header," and 64 bits for "data." QPI speeds are advertised by computing the transfer of 64 bits (8 bytes) of data every two clock cycles in each direction. ^[7]

Although the initial implementations use single four-quadrant links, the QPI specification permits other implementations. Each quadrant can be used independently. On high-reliability servers, a QPI link can operate in a degraded mode. If one or more of the 20+1 signals fails, the interface will operate using 10+1 or even 5+1 remaining signals, even reassigning the clock to a data signal if the clock fails.^[7]

The initial Nehalem implementation uses a single four-quadrant 25.6 GB/s link, which provides exactly double the theoretical bandwidth of Intel's 1600 MHz FSB used in the X48 chipset.

Contents 1 QuickPath Interconnect frequency specifications 2 See also 3 References 4 External links

[edit] QuickPath Interconnect frequency specifications

QPI operates at a clock rate of either 2.4GHz or 3.2GHz. The clock rate for a particular link depends on the capabilities of the components at each end of the links and the signal characteristics of the signal path on the printed circuit board. The Core i7 920 and 940 are restricted to a 2.4GHz frequency at stock reference clocks. Bit transfers occur on both the rising and the falling edges of the clock, so the transfer rate is double the clock rate.

Intel describes the data throughput (in GB/s) by counting only the 64-bit data payload in each 80-bit "flit." However, Intel then doubles the result because QPI is bidirectional. Thus, Intel describes a 20-bit QPI link with a 3.2Ghz clock as having a data rate of 25.6GB/s. A clock rate of 2.4Ghz yields a data rate of 19.2GB/s. More generally, by this definition a 20-lane QPI transfers eight bytes per clock tic, four in each direction.

The rate is computed as follows:

• 3.2GHz
• x 2 bits/Hz (double data rate)
• x 20 (QPI link width)
• x (64/80) (data bits/flit bits)
• x 2 (bidirectional)
• / 8 (bits/byte)
• = 25.6 GB/s

[edit] See also

• HyperTransport
• Intel X58
• List of device bandwidths

[edit] References

[edit] External links

• First Look at Nehalem Microarchitecture
• Ars Technica's What You Need To Know About Nehalem
• Everything You Need to Know About The QuickPath Interconnect (QPI)
• An introduction to Intel QuickPath Interconnect